FPGA Programming with Verilog

A Complete Guide from Digital Logic to Real-World Designs

Introduction: Hardware Is Different

1. What Is an FPGA?
2. Why Verilog?
3. What This Book Will Do
4. How to Read This Book
5. A Note on Conventions

Chapter 1: Bits, Numbers, and the Physical Layer

1. What Is a Digital Signal?
2. Binary, Hexadecimal, and Number Systems
3. Signed Representations: Sign-Magnitude, Ones Complement, Twos Complement
4. Boolean Values and Logic Levels
5. Voltage Thresholds, Noise Margins, and Real Hardware
6. Summary

Chapter 2: Boolean Algebra and Combinational Logic

1. The Basic Logic Gates
2. Boolean Algebra Laws and Identities
3. Truth Tables and Canonical Forms
4. Karnaugh Maps and Minimization
5. Combinational Hazards and Glitches
6. Summary

Chapter 3: Sequential Logic, Memory, and State

1. Latches versus Flip-Flops
2. The Clock Signal and Synchronous Design
3. Registers and Shift Registers
4. Counters and Timing Sequences
5. Metastability and Setup/Hold Time
6. Summary

Chapter 4: Hardware Thinking and Verilog Basics

1. Hardware Description versus Programming
2. Your First Verilog Module
3. Ports, Directions, and Data Types
4. Continuous Assignment and the assign Statement
5. What Synthesis Actually Means
6. Summary

Chapter 5: Combinational Logic in Verilog

1. Logical, Bitwise, and Reduction Operators
2. The always_comb Block
3. Conditional Assignment and if/else
4. Case Statements and Priority Encoders
5. Functions for Combinational Logic
6. Summary

Chapter 6: Sequential Logic in Verilog

1. The always_ff Block and Clocking
2. Blocking versus Nonblocking Assignments
3. Registers and Register Files
4. Counters and Timers
5. Reset Styles: Synchronous versus Asynchronous
6. Summary

Chapter 7: Inside an FPGA: What Your Code Becomes

1. The Configurable Logic Block
2. Look-Up Tables and Function Implementation
3. Routing Fabric and Timing
4. Embedded Memory Blocks and DSP Slices
5. Clock Management Resources and I/O Banks
6. Summary

Chapter 8: The Complete FPGA Development Workflow

1. Setting Up Your First Project
2. Simulation and Testbenches
3. Synthesis: From RTL to Netlist
4. Implementation, Place-and-Route, and Constraints
5. Bitstream Generation and Board Programming
6. Summary

Chapter 9: Finite-State Machines: The Heart of Control Logic

1. What Is a Finite-State Machine?
2. State Encoding Strategies
3. Moore versus Mealy Machines
4. The Three-Process FSM Style
5. FSM Timing, Reset, and Debugging
6. Summary

Chapter 10: Memories, FIFOs, and Data Structures

1. Inferred Combinational versus Registered Memory
2. Using Block RAM Resources
3. Read-Only Memory and Initialization Files
4. First-In First-Out Buffers
5. Memory-Mapped Address Decoding
6. Summary

Chapter 11: Timing, Resets, and Clock-Domain Crossing

1. Setup Time, Hold Time, and Critical Path
2. Timing Constraints and Reports
3. Reset Strategies and Power-On Initialization
4. Metastability and Synchronizers
5. Clock-Domain Crossing Techniques
6. Summary

Chapter 12: Serial Communication Protocols

1. Debouncing and Input Conditioning
2. Universal Asynchronous Receiver Transmitter
3. Serial Peripheral Interface
4. Inter-Integrated Circuit Protocol
5. Summary

Chapter 13: Display Interfaces and Video Generation

1. Seven-Segment Displays and Multiplexing
2. VGA Timing and Signal Structure
3. Generating Video Pixels at 25 MHz and Beyond
4. Summary

Chapter 14: Digital Signal Processing on FPGAs

1. Fixed-Point Number Representation
2. Multipliers and DSP Slices
3. Pipelining for Throughput
4. Finite Impulse Response Filters
5. Signal Processing Design Considerations
6. Summary

Chapter 15: System Integration and Soft Processors

1. Bus Protocols and Memory-Mapped I/O
2. Interconnecting Multiple Modules
3. Soft Processor Cores
4. Hardware-Accelerated Computation
5. Building a Complete System-on-Chip
6. Summary

Chapter 16: Optimization, Debugging, and Verification

1. Area versus Speed Tradeoffs
2. Timing Closure Strategies
3. In-System Debugging Tools
4. Verification Methodologies
5. Common Bugs and How to Avoid Them
6. Summary

Chapter 17: Professional RTL Design Practices

1. Synthesis-Friendly Coding Style
2. Parameterization and Reusability
3. Portability Across Vendor Tools
4. Version Control and Project Organization
5. From Hobbyist to Professional Engineer
6. Summary

Conclusion: What You Now Know

Glossary

References