Low Latency Programming in Java

Modern trading systems are won and lost inside the CPU. A thread scheduled onto the wrong core costs ten microseconds. A cache miss across NUMA nodes costs a hundred. These are not exotic hardware problems — they are software problems, and this book teaches you to fix them.

Working from the hardware up, this practical guide shows Java developers how to read CPU topology the way the scheduler sees it — cores, caches, sockets, and NUMA nodes — then pin threads to specific cores, eliminate context-switch jitter, and allocate memory on the node where it is actually used. Along the way you will learn to reason about cache hierarchies, execution pipelines, and SIMD without reaching for a profiler, and to measure and verify single-digit microsecond P99 latency rather than guessing at it.

You will learn to:

• Read CPU topology the way the scheduler sees it — cores, caches, sockets, NUMA
• Pin threads to cores and eliminate context-switch jitter
• Allocate memory on the NUMA node where it is used, not where it lands
• Reason about caches, pipelines, and SIMD without a profiler in hand
• Build systems with single-digit microsecond P99 latency — and verify it

Every example compiles against the open-source faster-hft-affinity library, and each printed sample is enforced by the companion repository's automated test suite. The book covers Linux, Windows, and macOS, and includes complete working implementations of NUMA-aware data structures, thread pools, and market data gateways.

Written for engineers building high-frequency trading systems, real-time market data infrastructure, and any application where predictable, minimal latency separates success from failure.