From Bare-Metal Fundamentals to Production-Ready Firmware
- About This Book
Introduction: The STM32 Universe
Chapter 1: ARM Cortex-M Architecture and the STM32 Platform
- The ARM Cortex-M Processor Family
- Instruction Set: Thumb-2 and Pipeline Architecture
- Registers, Stack, and the Programmer’s Model
- Nested Vectored Interrupt Controller (NVIC)
- System Control Block (SCB) and SysTick Timer
- STM32 Bus Matrix: AHB, APB, and Memory Mapping
Chapter 2: STM32 Families and Device Selection
- The Naming Convention Decoded
- Mainstream Series: F0, F1, F3, F4, F7
- High-Performance Series: H7, H5, U5
- Ultra-Low-Power Series: L0, L4, L5, U0
- Specialized Series: G0, G4, N6, WB, WL, C0, C5
- Selection Matrix: How to Choose Your MCU
Chapter 3: Development Environments and Toolchains
- STM32CubeIDE: The Official Integrated Environment
- STM32CubeMX: Peripheral Configuration and Code Generation
- GCC Cross-Compiler and Makefile-Based Workflows
- Keil MDK-ARM and IAR Embedded Workbench
- OpenOCD, ST-Link Utilities, and Command-Line Tooling
- Project Templates and Build System Comparison
Chapter 4: CMSIS, HAL, LL Libraries, and Software Architecture
- CMSIS Core: The ARM Standard Interface Layer
- Device-Specific CMSIS: Peripheral Register Definitions
- HAL Library: Abstraction with Trade-offs
- LL (Low-Layer) Library: Speed Meets Readability
- Building Your Own Hardware Abstraction Layer
- Software Architecture Patterns for Production Firmware
Chapter 5: Bare-Metal Programming, Memory, and Boot Process
- Memory Map: Flash, SRAM, Peripheral Registers
- The Linker Script: Defining Memory Sections
- Startup Code: Vector Table and Reset Handler
- Boot Modes: System Memory, Main Flash, SRAM
- First Bare-Metal Program: Blinking an LED Without Libraries
- Building a Minimal Project from Scratch
Chapter 6: Clock Configuration and GPIO
- Clock Sources: HSI, HSE, CSI, LSI, LSE
- PLL Configuration and System Clock Tree
- Bus Prescalers and Flash Wait States
- GPIO Modes: Input, Output, Alternate Function, Analog
- Pull-Up/Pull-Down Resistors and Drive Strength
- Complete Project: Clock Setup + LED Blink + Button Read
Chapter 7: Interrupts, Timers, PWM, and Watchdogs
- EXTI Lines and Interrupt Priority Grouping
- General-Purpose Timers: Basic Timebase
- Output Compare and PWM Generation
- Input Capture and Encoder Interface Mode
- Advanced Timers: Complementary PWM and Dead-Time
- Independent and Window Watchdog Timers
Chapter 8: DMA, ADC, DAC, and Analog Peripherals
- DMA Architecture: Streams, Channels, and Priorities
- Memory-to-Memory and Peripheral Transfers
- ADC Modes: Single, Scan, Continuous, Injected
- ADC with DMA: Multi-Channel Sampling
- DAC Output and Waveform Generation
- Analog Comparators and Operational Amplifiers
Chapter 9: Communication Peripherals I – UART, SPI, and I2C
- USART/UART: Asynchronous Serial Communication
- Hardware Flow Control and DMA for Serial
- SPI: Master Mode with DMA Transfer
- SPI: Slave Mode and Multi-Master Considerations
- I2C: Master Transmitter and Receiver Modes
- I2C: SMBus, Clock Stretching, and Troubleshooting
Chapter 10: Communication Peripherals II – CAN, USB, Ethernet, SDIO, QSPI
- CAN Bus: Frame Types, Filters, and Bit Timing
- CAN FD and Dual CAN Controllers
- USB Device: CDC, HID, and Mass Storage Classes
- USB OTG Host and Device Modes
- Ethernet MAC with DMA (EMAC)
- SDIO, QSPI, and External Memory Interfaces
Chapter 11: Real-Time Operating Systems – FreeRTOS on STM32
- RTOS Fundamentals: Tasks, Priorities, and Preemption
- Setting Up FreeRTOS with CMSIS-RTOS v2
- Task Creation, Management, and Lifecycle
- Inter-Task Communication: Queues, Semaphores, Mutexes
- Event Groups and Software Timers
- RTOS Integration with HAL and Hardware Peripherals
Chapter 12: Low-Power Modes and Power Optimization
- Sleep Mode: CPU Idle with Peripheral Activity
- Stop Modes: VCO Shutdown and Wake-Up Sources
- Standby and Shutdown Modes: Deepest Power Savings
- Voltage Scaling and Dynamic Frequency Scaling
- Tickless Idle in FreeRTOS
- Complete Project: Battery-Powered Sensor Node
Chapter 13: Bootloaders, Firmware Updates, and Flash Programming
- System Memory Bootloader (ROM Loader)
- In-Application Programming (IAP) Architecture
- Custom Bootloader Design: Vector Table Relocation
- A/B Firmware Slots and Rollback Protection
- Device Firmware Upgrade (DFU) Protocol
- Over-the-Air (OTA) Update Strategies
Chapter 14: Debugging, Profiling, and Testing
- ST-Link Debugger: SWD vs JTAG
- GDB Remote Debugging with OpenOCD
- Hardware Breakpoints, Watchpoints, and Trace
- ITM and Semihosting for Debug Output
- Performance Profiling: Cycle Counters and Cache Analysis
- Unit Testing and Hardware-in-the-Loop Strategies
Chapter 15: Security Features and TrustZone
- Flash Protection: Readout Protection (RDP) Levels
- Memory Protection Unit (MPU) Configuration
- Arm TrustZone for Cortex-M33 Devices
- Hardware Cryptography: AES, HASH, TRNG, RSA/ECC
- Secure Boot and Trusted Execution Environments
- STM32Trust Framework and PSA Certified
Chapter 16: Performance Optimization and Production Best Practices
- Compiler Optimizations: -O2, -Os, LTO, and Link-Time
- Cache Management: ICACHE, DCACHE, and Prefetch
- DTCM and CCM SRAM for Time-Critical Code
- Fault Handlers and HardFault Debugging
- Error Handling Patterns and Assert Strategies
- Production Checklist: From Prototype to Volume Manufacturing