Processor Architecture with Rust

Understanding The Processor Through Rust

You write Rust. You care about performance. But do you know what happens after the compiler is done?

Your code compiles to machine instructions that run on real silicon — through pipelines, caches, branch predictors, and execution units that have their own rules, their own bottlenecks, and their own surprises. A single line change can make a loop run 10x faster. A struct reordering can cut memory traffic in half. A branchless rewrite can eliminate a stall that costs millions of cycles per second.

These aren't compiler tricks. They're hardware effects. And most Rust programmers have never learned them.

What's inside

Part I — The Machine Under Your Code starts at the transistor and builds up. Logic gates, adders, flip-flops, the ALU, registers, the memory hierarchy, caches, instruction pipelines, branch prediction, out-of-order execution, and multi-core parallelism. No electrical engineering required — just clear explanations, diagrams, and Rust examples that connect every hardware concept to code you'd actually write.

Part II — Writing Rust That Respects the Hardware takes what you learned and puts it to work. Data layout for cache performance. Branchless programming. SIMD. Memory access patterns. Concurrency primitives mapped to hardware operations. Profiling with real tools. Four case studies that take naive code, profile it, find the bottleneck, and optimize — with measurements at every step.

21 chapters. 5 appendices. From silicon to cargo bench.

Table of contents

Part I — The Machine Under Your Code

1. Why Should You Care?
2. Bits, Gates, and How Computers Think
3. The ALU — The Calculator Inside
4. Registers — The Fastest Memory You'll Never See
5. The Memory Hierarchy — A Story of Trade-offs
6. How the Cache Actually Works
7. The Instruction Cycle — Fetch, Decode, Execute
8. The Instruction Pipeline — An Assembly Line for Instructions
9. Branch Prediction — Guessing the Future
10. Out-of-Order Execution and Superscalar Design
11. Multi-Core and Parallelism

Part II — Writing Rust That Respects the Hardware

12. From Rust to Machine Code — The Compilation Pipeline
13. Data Layout and Cache Performance
14. Branching in Practice
15. SIMD in Rust
16. Memory Access Patterns
17. Concurrency and the Hardware
18. Alignment, Allocation, and the OS
19. Profiling and Measuring
20. Case Studies
21. Zero-Copy by Default — Rust's Hidden Performance Advantage

Appendices: x86-64 Assembly Cheat Sheet, ARM64 Assembly Cheat Sheet, Glossary, Tools Reference, Further Reading